Use SSE2 intrinsics to allow the Cray compiler to work.

asio/include/asio/detail/gcc_x86_fenced_block.hpp

diff --git a/asio/include/asio/detail/gcc_x86_fenced_block.hpp b/asio/include/asio/detail/gcc_x86_fenced_block.hpp
index fc64cd7..9a71a53 100644
--- a/asio/include/asio/detail/gcc_x86_fenced_block.hpp
+++ b/asio/include/asio/detail/gcc_x86_fenced_block.hpp
@@ -63,7 +63,11 @@
   static void lbarrier()
   {
 #if defined(__SSE2__)
+# if (__GNUC__ >= 4)
+    __builtin_ia32_lfence();
+# else // (__GNUC__ >= 4)
     __asm__ __volatile__ ("lfence" ::: "memory");
+# endif // (__GNUC__ >= 4)
 #else // defined(__SSE2__)
     barrier();
 #endif // defined(__SSE2__)
@@ -72,7 +76,11 @@
   static void sbarrier()
   {
 #if defined(__SSE2__)
+# if (__GNUC__ >= 4)
+    __builtin_ia32_sfence();
+# else // (__GNUC__ >= 4)
     __asm__ __volatile__ ("sfence" ::: "memory");
+# endif // (__GNUC__ >= 4)
 #else // defined(__SSE2__)
     barrier();
 #endif // defined(__SSE2__)